In the field of integrated circuit (IC) devices, using only N-channel MOSFET (metal oxide semiconductor field effect transistor) devices, also known as NMOS devices, is a common cost reduction method due largely to die size reduction, as well as due to other benefits. However, using NMOS devices in place of PMOS (P-channel MOSFET) devices typically involves the NMOS device being positioned on a ‘high side’ of a load, where the NMOS device is located between the load and the supply voltage rail. When the NMOS device is in a fully ‘open’ state (i.e. in saturation mode in which current is able to flow freely through the NMOS device), the source node is effectively coupled to the supply voltage rail via the open NMOS device. In order to achieve a fully open state, a significant positive voltage (VGS) across the gate and source nodes is required in order to bias the NMOS device into saturation mode. To achieve this, the gate voltage must be greater than the drain voltage (i.e. the supply rail voltage) by at least the threshold voltage level (Vth). Clearly, where the supply rail voltage is the highest available supplied voltage signal, some means of generating a higher voltage level is required.
To this end, it is known to use a bootstrap charge storage device, such as a bootstrap capacitor, to generate the higher voltage level. FIG. 1 illustrates a simplified circuit diagram of an example of a DC (direct current) motor driver circuit 100 comprising a high-side NMOS device 110 and a bootstrap capacitor 120. The gate node voltage of the NMOS device 110 is generated by a control signal 130 passed through gate control circuitry, which in the simplified example of FIG. 1 is illustrated as comprising buffer logic 140. A negative supply rail for this buffer logic 140 is operably coupled to the source node 112 of the NMOS device 110, and a positive supply rail 144 for this buffer logic 140 is operably coupled to the negative supply rail 142 via the bootstrap capacitor 120. In this manner, ‘floating’ supply voltage rails are provided to the buffer logic 140, with the negative rail voltage being tied to the source voltage of the NMOS device 110, and the positive rail voltage being determined by the voltage across the bootstrap capacitor 120. Accordingly, by maintaining a suitable charge within the bootstrap capacitor 120, it is possible to generate a gate voltage sufficiently high to force the NMOS device 120 into its saturation mode.
In a typical intermittent driver mode (e.g. 100 ms on, 100 ms off), the bootstrap capacitor 120 discharges during the off state of the driver circuit 100. Accordingly, it is necessary to compensate for such discharging of the bootstrap capacitor 120 in order to maintain a large enough charge therein to generate a gate voltage sufficiently high to force the NMOS device 120 into its saturation mode. In such a conventional driver circuit 100 comprising such a bootstrap capacitor 120, a charge pump 150 is typically provided and arranged to inject some current into the bootstrap capacitor 120 during the off state of the driver circuit 100. In this manner, a suitable charge within the bootstrap capacitor 120 may be maintained.
Recently, requirements for such driver circuits have stipulated that no power consumption may occur during the off state of the driver circuit 100. As such, the use of such a charge pump 150 during an off state of the driver circuit 100 is not permitted under such customer requirements. Accordingly, the use of such a charge pump 150 would be limited to during the on state of the driver circuit 100. However, because of the inherent charge loss within the bootstrap capacitor during the off state of the driver circuit 100, there will be an initial period during the on state of the driver circuit 100 in which the bootstrap capacitor 120 is required to be recharged. During such an initial period, an insufficiently high bias voltage will be available to fully turn on the NMOS device 110, resulting in increased current limitation within the NMOS device 110 during that initial period, and thus increased heat generation within the NMOS device 110, which is undesirable and in some cases may be unacceptable.